Noise and Variation Tolerant Multilevel Memristor Memory (MLMM) Systems, MRAM macros for Memory-in-Logic

Memristor related papers and abstracts from the 20th Great Lakes symposium on VLSI (May 16 – 18, 2010):

Design considerations for variation tolerant multilevel CMOS/Nano memristor memory (Harika Manem, Garrett S. Rose, Xiaoli He, Wei Wang) examines, in part, unfolded crossbar memory noise margins and power consumption:

“This work analyzes the design constraints for nanoscale multilevel memristive memory arrays, in particular the noise margin, and provides two alternative hybrid approaches that successfully eliminate sneak paths and provide better noise and variation tolerance.” [ACM Abstract and Access]

Design of embedded MRAM macros for memory-in-logic applications (Sumanta Chaudhuri, Weisheng Zhao, Jacques-Olivier Klein, Claude Chappert, Pascale Mazoyer ) looks at simulation results of hybrid MTJ-CMOS design methods for integrating non-volatile MRAM memory cells into CMOS:

“…with examples of automatic macro generation, integration layout and a prototype in 130nm CMOS, [x] designed to test a large subset of this design space. In conclusion we show that a high 3D integration density with reasonable speed can be achieved with automatic flow by sharing the reading/writing circuitry among a number of MTJs.” [ACM Abstract and Access]