IEEE Symposia on VLSI Technology and Circuits 2012

The IEEE Symposia on VLSI Technology and Circuits, from June 12 to 15 in Honolulu, Hawaii will have several in depth tracks focusing on ReRam and memristor based research. The two tracks have the following tentative schedules: please bookmark and check the VLSI Conference Website (below) for the latest updates and information. A sampling of the current memory lineup includes:

Monday, 6/11: Technology Short Course: 14nm CMOS Technology & Design Co-Optimization and Emerging Memory Technologies

  • FinFET – History Fundamentals and Future, T-J King Liu , UC Berkeley, USA
  • FinFET Design Enablement – Foundry Perspective, B. Sheu,TSMC, Taiwan
  • Heterogeneous CMOS Integration, S. Takagi , Univ. of Tokyo, Japan
  • Interconnect Technology, M. Angyal , IBM, USA
  • Advanced Patterning, H. Levinson, GLOBALFOUNDRIES, USA
  • Emerging Memory Technology, G. H. Koh, Samsung, Korea

Tuesday, 6/12: Technology Track

  • Advanced Fin FET Devices and Technology
  • NAND Flash
  • High-K / Metal Gate Scaling
  • Alternative Memory
  • Low Power and Steep Subthreshold Technology
  • STT MRAM
Tuesday, 6/12: Circuits Track:  Ultra Low Power SoC Design for Future Mobile Systems:
  • Vision of Future Mobile Systems – Jan Rabaey, UC Berkeley
  • Low-Power Logic Design Technologies – Masaya Sumita, Panasonic
  • Memory Architecture and Systems for Mobile Systems – Kyomin Sohn, Samsung
  • Wireless Communication – Gangadhar Burra, Texas Instruments
  • Interconnect and Wireline Communication – Jared Zerbe, Rambus
  • Case-Study on Low-Power Mobile System – John Redmond, Broadcom
Tuesday, 6/12: Circuits Track:  Designing in Advanced Cmos Technologies
  • Bulk CMOS Scaling to the End of the Roadmap – Tsu-Jae King Liu, UC Berkeley
  • Technology Boosters for LP Design Platforms in 28/20nm – Thomas Skotnicki, STMicroelectronics
  • Challenges and Solutions Paths in Scaling SRAM – Fatih Hamzaoglu, Intel
  • The Mixed-Signal Design Challenges in the Advanced Technology Nodes – Fu-Lung Hsueh, TSMC
  • Power-aware Design in 28nm Generation and Beyond-Facts, Myths, and Misunderstandings – Youngsoo Shin, Kaist
  • Advanced CAD Methodologies for Custom Design at Advanced Process Nodes – David White, Cadence R&D

Wednesday, 6/13: Technology Track

  • RRAM I
  • Process Technology
  • Technology / Circuits Joint Focus Session – Memory
  • Mobility Enhancement
  • Technology / Circuits Joint Focus Session – 3D-System Integration
  • Technology/Circuits Joint Focus Session – Emerging Nonvolatile Memory
  • Ultra-Thin Body Devices
  • Novel Passive and Active BEOL Technologies


Thursday, 6/14:  Technology Track

  • Technology/Circuit Joint Focus Session – Advanced SRAM
  • SCMOS Platform
  • Noise Phenomena
  • Technology / Circuits Joint Focus Session – Design in Scaled Technologies
  • RRAM II
  • Technology and Circuits Joint Luncheon Talk
  • Technology/Circuit Joint Focus Session – Design Enablement in Scaled CMOS
  • High Mobility – Ge Devices
  • 3D Integration Technology
  • Technology/Circuit Joint Focus Session – Embedded Memory
  • SScaled III-V Transistors and Modeling
  • Variability Characterization and Modeling

You can find the latest technology track information HERE (vlsisymposium.org) , and the latest Circuit Track information HERE (vlsisymposium.org).

The Conference Website is at vlsisymposium.org. The dates are June 12-15. The Symposia on VLSI Technology and Circuits is sponsored by the IEEE Electron Devices Society, the Solid State Circuits Society, and the Japan Society of Applied Physics.

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